As for Panzer88's reply I agree. I don't know if I can say they painted themselves into a corner but they seem to act like they have where others are reaping the rewards of playing nice with others. I liked that talk as well, even linked it round here a few months back http://www.romhacking.net/forum/index.php/topic,21667.0.html and highly suggest it for all replying here, probably not before you watch https://www.youtube.com/watch?v=K5miMbqYB4E but makes a nice double bill.
I hadn't seen the thread until now. I'll listen soon.
Back on volumes I am sitting here wondering if the cheap and cheerful silicon fab places (others reading some of the much larger process sizes, because it is not like this will need something crazy small, have been reduced to the levels which mere mortals can just about afford to use if you know where to look).
This part is pretty confusing to me. I'd appreciate a clearer statement? I have worked with FABs, including those who broker their services, and I'm not sure exactly what you are wanting to say here. I get the "volumes" part and how that may relate to a FAB. But what exactly are you thinking about?
Now I'll try and read between the lines. I think you are saying that high volumes and FAB production goes hand-in-hand. So if you are talking about high volumes, then it is perfectly reasonable to consider accessing a FAB process. So far, that's true.
Note: I'd add that even if you are talking about relatively small volumes, it can make sense to consider accessing a FAB. FABs need to run pretty much 24/7, if possible. A FAB owner may (if they aren't a top of the line FAB used by a major chip supplier, anyway) only need their FAB for 12 hours a day (or less.) And they want to sell the remaining time. For a long time now, there are brokers who specialize in selling access to such FABs. And you can even do this on a "single wafer" run, too, at reasonable costs. I bought a single wafer and processing for $5k, some years back, in fact. There are other costs -- cutting the wafer into dies, testing the dies and binning them, wire bonding them into packages, and so on. But the point here is that you don't even need high volume anymore to reasonably consider a custom ASIC design FAB'd on a brokered FAB process somewhere. It's done all the time.
It is also true that the highest end FABs, those FAB processes which provide unique advantages to their owners, pretty much are NEVER brokered to anyone. This is the problem that faced MIPS, for example, when it wanted to field the then-new R2000 series parts. To compete with Intel and Motorola, who at the time were FABing out their high end chips to a buying market, MIPS couldn't access their FAB processes because neither of them would sell any time. So MIPS had to use processes which had about 1/10th the number of equivalent gates (inverters and transmission lines) and had of course much larger feature sizes, as well, and so were slower (or at the same gate count and clock rates would be lots more power hungry.) This was a huge hurdle to climb over. But they managed to do quite well at the time, given that they only had access to third tier, rather old FAB processes. The story here is that only the owners of the very best FAB processes get to use those processes. If you are shopping around for brokered FAB time, then you get to use 2nd or 3rd tier older equipment and processes. But at least they are mature and fairly cheap.
You and I, assuming we could pony up a few tens of thousands of dollars, could have access to appropriate software and FAB capacity. Nintendo, of course, could access much better processes with many more processing steps and much smaller features. But the NRE (non-refundable engineering) investment would be a lot higher, of course. But the 65C816 (about 22000 transistors) or 6502 (3510 transistors) are VERY SMALL devices to produce. On the better FABs, processing 12" wafers and using somewhat older 90nm feature sizes, you might expect to get a 10 million 6502s from a single wafer, as a rough guess. The early 6502 used 8000nm features and occupied 21mm^2 in area. They sucked up about 60mA at 5V, too, running at 1MHz -- about 300mW. At the 90nm feature size, and assuming other things don't change in a re-FABd design -- they would, though), the new die size would be about 0.0025 mm^2, or about 10,000 times smaller in area. Other things being the same, this would imply 10,000 less capacitance being switched. The power supply voltage could be as little as 1V, but probably would "like" 1.2V. (With typical I/O wanting more like 3V, that might imply some "additions" to work this all out.) But the basic idea is that the new power requirement would be lower by a factor of about 1.2/5/10000, or about 7 microwatts total. However, it's even better than that because NMOS chews up a LOT more power than CMOS. In any case, you'd expect that die to have less than the expected leakage of a typical CR2025 lithium button battery kept on the shelf and unused. In short, you could run that CPU on a lithium battery for about the same time as is the long term shelf life of that same battery. There is no question you could run it for about ten years at least, that way. Of course, there is more to make it useful. That that's a thumbnail sketch of where Nintendo could reach towards, if they wanted to, with an NES cpu. (The power estimates are assuming a clock rate at 1MHz... (the new feature sizes would allow MUCH faster rates, too, of course.)
For a benchmark, keep in mind that about 1/3rd of the current FAB capacity is at 40nm or smaller! So 90nm is almost "easy" these days. About a quarter of the FAB capacity is running at 80nm to 200nm. You and I could probably buy 200nm features, if we shopped around, at rates even a hobbyist might be able to muster. And at 400nm or so, I'm sure of it. And the power requirements would still be very, very low, and the supportable clock rates still far higher than we'd need. If any of us wanted to do a short "run" of chips at larger feature sizes, it would still beat the pants off of those older parts in every meaningful way.